Various types of silicon transistors often include a polysilicon gate. There are many factors that can influence the proper height of the gate. For example, making the gate too tall can cause problems such as undesirable parasitic capacitance in the final product, as well as implant shadowing problems (especially where gates are repeated at a small scaled pitch) and difficulties in polysilicon etching during manufacturing. Thus, it is desirable to limit the height of the polysilicon gate.
On the other hand, making the gate too short can introduce other problems. For example, during transistor manufacture, there is a trade-off between either allowing for undesirable boron penetration into the transistor channel or insufficiently doping the source/drain regions of the transistor. For example, referring to FIG. 1, an illustrated conventional silicon device has a silicon-on-insulator (SOI) wafer configuration that includes a silicon body 1, a buried oxide (BOX) layer 4 immediately under silicon body 1, and a substrate (not shown) under BOX layer 4. The device has a transistor that includes a polysilicon gate 2 and a source/drain region 3. To create source/drain region 3, that region is doped with boron ions. Gate 2 is also simultaneously doped with boron ions. In FIG. 1, to avoid penetration of the boron ions into the channel below gate 2, a low energy dose of boron ion is used. While successfully avoiding channel boron penetration, the side effect of such a low energy dose is that source/drain region 3 is not fully doped such that it abuts BOX layer 4. In other words, there is a gap between the source/drain regions 3 and BOX layer 4. This can lead to an undesirably high junction capacitance.
Referring to FIG. 2, this time a higher energy dose of boron ions is used. As a result, source/drain region 3 is now properly abutted to BOX layer 4, thus reducing the junction capacitance. However, in order to fully dope source/drain region 3, a side effect is that boron ions have penetrated fully through gate 2 into the channel portion of silicon body 1 below. Such channel boron penetration results in extensive degradation of channel mobility, which is quite undesirable. Consequently, there is a need for a way to fully dope a transistor source/drain region without allowing an undesirable amount of boron ions to penetrate into the channel.
In addition, it has been found that the use of a silicon-germanium (SiGe) layer on opposing sides of the gate and channel of a transistor can greatly improve the performance of the transistor. This is caused by the compressive forces placed on the channel by the SiGe layer. It would therefore also be desirable to find a way to manufacture a transistor including such an SiGe layer, yet additionally fully dope the source/drain region without while minimizing or otherwise reducing channel boron penetration.